The invention relates to an address transition detection(ATD) circuit of a memory device, and more particularly to an address transition circuit capable of preventing the malfunction caused by wrongly interpreting noises as normal ATD pulses. This is achieved by generating different ATD pulses for normal operation state and noise induced operation state.
Many types of address transition detection techniques exist, and they are widely used in semiconductor memory devices. Basically, however, an address transition detection is a technique that generates one pulse by detecting the changed address input every time an address input changes. ATD pulses made from each address are combined and are used for precharging, equalizing, and sense-enabling of the internal circuit of semiconductor devices. As shown in FIG. 1, a conventional address transition detection circuit is constructed with an input control unit 1 that includes an inverter I1 and a NOR gate NOR1 into which address signals A and chip select signals CS are input; a delay/inversion unit 2 that delays and inverses output signals B from the said input control unit 1 using sequentially arranged inverters I2, I3, I4; another delay/inversion unit 3 that delays, inverses, and outputs inverted output signals E of the said input control unit 1 using sequentially arranged inverters I6, I7, I8, after the signal B pass through an inverter 15; and a logic combination unit 4 having a NOR gate NOR2 that performs NORing after receiving output signals C of the said delay/inversion unit 2 and output signals B of the said input control unit 1, a NOR gate NOR3 that performs NORing after receiving output signals E of the said another delay/inversion unit 3 and inverted output signals F of the said input control unit 1, and a NOR gate NOR4 that performs NORing on output signals D and G of the said two NOR gates NOR2, and NOR3 and outputs them as ATD pulse signals .phi.AT.
In the following section, the conventional technique is explained in detail by referring to the operation timing diagrams given in FIG. 2 and FIG. 3.
First, when in normal operation state as in FIG. 2, address signals A given in (a) of FIG. 2 are input and then delayed signals B given in (b) of FIG. 2 are output through a NOR gate NOR1 and an inverter I1. Then, at the delay/inversion unit 2, these signals B are output as delayed/inverted signals C given in (c) of FIG. 2, using serially connected odd-numbered inverters 12,13,14. Then, a NOR gate NOR2 performs NORing on the said signals B, C and generates signals D given in (d) of FIG. 2. On the other hand, the output signals B of the said input control unit 1 are output as inverted signals E given in (e) of FIG. 2 by an inverter IS. Then, this signal is output as delayed/inverted signals F by serially connected odd-numbered inverters I6-I8. Then, a NOR gate NOR3 performs NORing on the said signals E, F to generate output signals G given in (g) of FIG. 2. Output signals D and G of the NOR gates NOR2, and NOR3 are NORed again at a NOR gate NOR4 and then ATD pulses .phi.AT given in (h) of FIG. 2. are generated.
FIG. 3 illustrates a noise induced operation state where noise pulses are generated. The waveform illustrated on the left side of the drawing indicates the case where noise pulses in low state are generated and the waveform illustrated on the right side of the drawing indicates the case where noise pulses in high state are generated. Here, for the sake of convenience, the case where noises in low state are input will be explained. When noises of low pulses given in (a) of FIG. 3 enter as inputs, they go through an input control unit 1 and a delay/inversion unit 2. Then, noises of high pulses given in (d) of FIG. 3 appear at the NOR gate (NOR 2). On the other hand, output signals of the input control unit 1 pass through an inverter I5 and become inverted, and then they pass through the delay/inversion unit 3. Then, they are inut into a NOR gate NOR3. Accordingly, at the output of the NOR gate NOR3, noises of slightly delayed high pulses given in (g) of FIG. 3 appear. As a result, the final outputs of the address transition detection circuit that are output after NORing the outputs of NOR gates NOR2 and NOR3 appear as pulses having a certain width and overlapped noises of low pulses as shown in (h) of FIG. 3.
If we compare these with the ATD pulses generated during the normal operation state which are given in (h) of FIG. 2, we find that the noise pulses having almost the same width as normal ATD pulses are generated and that the internal circuit may therefore mis-interpret noise pulses as normal ATD pulses. In other words, the above prior art address transition detection circuit, when in a normal operation state or an induced operation state, generates the same signals. Accordingly, unwanted ATD pulses are generated by noises and the internal circuit related to these are activated, thus causing malfunctions such as reading the wrong data.